Qianyu CHENG (程 乾宇) @ USTC

High Energy-Efficient Intelligent Computing Lab, Suzhou Institute for Advanced Research, USTC
Email: qycheng AT mail.ustc.edu.cn

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Qianyu Cheng is currently a Ph.D. candidate and a member of the High Energy-Efficient Intelligent Computing Lab, University of Science and Technology of China (USTC), supervised by Prof. Huaping Chen and Prof. Chao Wang. Before that, Cheng received his bachelor’s degree (honor program) from the University of Electronic Science and Technology of China (UESTC) in 2022.

His research interests include CPU-FPGA heterogeneous systems, distributed accelerator systems, and their application on large-scale analytical processing and multi-tenant cloud service. Besides, he is also interested in virtualization technology for accelerators and heterogeneous systems.

NEWS

Mar 25, 2025 Two short papers are accepted by DAC 2025. Congrats to Jinao and Jiajun!
Mar 21, 2025 One paper is accepted by ICME 2025. Congrats to Cheng Tang!
Aug 01, 2024 Two paper are accepted by ICCD 2024.
May 30, 2024 Two papers are accepted by FPL 2024.
May 13, 2024 Successfully pass the oral qualifying exam. Ph.D. candidate now!
Apr 14, 2024 A paper is accepted by FCCM 2024 Ph.D. forum.
Mar 04, 2024 Our routing toolchain led by Wenbin Teng won the 5th place in the Runtime-First FPGA Interchange Routing Contest, FPGA 2024.
Nov 03, 2023 Invited to share our research work at Hohai University.
Aug 03, 2023 An accelerator based on emerging AI Engine hardware, codesigned with Zhendong Zheng and Binze Jiang, won the 2nd runner-up in the Customized Computing Challenge, CCFSys 2023.
Aug 10, 2022 Invited to present our toy project in AMD-Xilinx China Summer Camp, 2022 (hosted by CCF Technical Committee on Computer Architecture).

EDUCATION

  • Sep 2022 - Present, School of Computer Science and Technology, University of Science and Technology of China, Hefei, Anhui, China
    • Ph.D. candidate in Computer Engineering (successive master-doctoral program)

  • Sep 2018 - Jun 2022, Yingcai Honors College, University of Electronic Science and Technology of China, Chengdu, Sichuan, China
    • B.Sc. in Computer Science and Technology
    • Thesis: The Design of RISC-V Dynamic Branch Predictor for Neural Network Workload (Outstanding Bachelor Thesis Award, Top 14/391)

HONORS & AWARDS

  • Mar 2024, USTC-Suzhou Industrial Park Scholarship.

  • Dec 2023, National Scholarship for Postgraduate Students.

  • Jun 2022, Outstanding Graduate in UESTC.

PUBLICATION

  1. DAC’25
    Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
    Jinao Li, Wang Teng, Qianyu Cheng, Zhendong Zheng, Lei Gong, and 3 more authors
    In The 62nd Design Automation Conference , Jun 2025
  2. DAC’25
    Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
    Qianyu Cheng, Jiajun Ji, Teng Wang, Zihan Wang, Lei Gong, and 2 more authors
    In The 62nd Design Automation Conference , Jun 2025
  3. ICME’25
    Spectral Enhanced Tuning: A Plug-and-Play Framework for Dehazing Models with Frequency Decoding and Fusion
    Cheng Tang, Wenqi Lou, Qianyu Cheng, Jiayi Tuo, Wei Fu, and 3 more authors
    In IEEE International Conference on Multimedia & Expo 2025 , Jun 2025
  4. ICCD’24
    UniCoMo: A Unified Learning-Based Cost Model for Tensorized Program Tuning
    Zihan Wang, Lei Gong, Wenqi Lou, Qianyu Cheng, Xianglan Chen, and 2 more authors
    In The 42nd IEEE International Conference on Computer Design , Nov 2024
  5. ICCD’24
    AutoSparse: A Source-to-Source Format and Schedule Auto-Tuning Framework for Sparse Tensor Program
    Xiangjun Qu, Lei Gong, Wenqi Lou, Qianyu Cheng, Xianglan Chen, and 2 more authors
    In The 42nd IEEE International Conference on Computer Design , Nov 2024
  6. FPL’24
    SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs
    Qianyu Cheng, Zhendong Zheng, Cheng Tang, Tianhao Jiang, Teng Wang, and 4 more authors
    In The 34th International Conference on Field-Programmable Logic and Applications , Sep 2024
  7. FPL’24
    Lora: A Latency-Oriented Recurrent Architecture for GPT on Multi-FPGA with Communication Optimizaion
    Zhendong Zheng, Qianyu Cheng, Teng Wang, Lei Gong, Xianglan Chen, and 3 more authors
    In The 34th International Conference on Field-Programmable Logic and Applications , Sep 2024
  8. FCCM’24
    Ph.D. Project: Optimizing the Data Traffic for Large Graph Processing on FPGA via a Stateful Approach
    Qianyu Cheng, Teng Wang, and Chao Wang
    In IEEE 32st Annual International Symposium on Field-Programmable Custom Computing Machines , May 2024